Accompanying the popularization of portable telephones, portable computers, and other small electronic devices, the demand for increasingly miniaturized and thinner devices which contain semiconductor elements has increased. In order to answer this demand, the BGA package and the CSP package have been developed and put into practical use. For example, in Japanese Kokai Patent No. Hei 11[1999]-345837, a method for the manufacture of a BGA package is disclosed in which the semiconductor chip is a flip chip or is made to face down, and an underfilling processing is performed between the substrate and the semiconductor chip.
In the case of the flip-chip mounting of a semiconductor chip, on the substrate side, wire patterns are formed that correspond with the electrode pads or the electrode bumps of the semiconductor chip. If the wiring pitch and the electrode pitch on top of the semiconductor chip are made small, the pitch and the surface area of the wiring pattern on the substrate side corresponding to it must be made small.
In the case of flip-chip mounting, for example, as shown in FIG. 7(a), on the rear surface of a semiconductor chip 10 stud bump electrodes 12 are formed at a pitch (P); and on the other hand, on top of a substrate 16, a copper pattern 14 is formed to correspond to said pitch (P), and on top of the copper pattern 14, a solder plating 18 is formed; both are bonded by projecting the stud bump electrodes 12 into the solder plating 18. The bonded section is aligned by melting the solder plating 18. Also, if the semiconductor chip 10 is miniaturized, the pitch (P1) of the stud bump electrodes 12, as shown in FIG. 7(b), becomes narrow, and the pitch and line width of the copper pattern 14 are made small accordingly.
The method of forming the solder plating on top of the copper pattern is explained as follows. As shown in FIG. 8(a), the copper pattern 14 is formed with a constant pitch on top of the substrate 10. On this copper pattern 14, a wide region 14a is formed. Next, as shown in FIG. 8(b), a solder mask 20 is formed on top of the substrate. Apertures 22 are formed in the solder mask 20, and the portions of the copper pattern 14 containing the wide region 14a are exposed by the apertures 22. Next, as shown in FIG. 8(c), a powder or granular form of solder 24 is adhered on top of the copper pattern 14 through the apertures 22 of the solder mask 20.
FIG. 8(d) depicts a cross-sectional view of FIG. 8(c) through line X-X. The granular solder 24 is adhered approximately uniformly on the exposed copper pattern 14. Next, as shown in FIG. 8(e), the solder 24 is reflowed at a temperature. Because the surface area of the wide region 14a is greater than the surface area of the other regions, the majority of the solder collects in the wide region 14a; and the melted solder forms the solder protrusions or bumps 26 at the wide region 14a due to its surface tension.
When solder plating is formed with this method, there are the following problems. The copper pattern 14 on top of the substrate is formed by an etching process using a mask, or by an electroless plating method. Either way, there are limits to the processing precision of the copper pattern. And if the pitch of the copper pattern is made less than 40 μm, as shown in FIG. 9 (a), it is difficult to control the spacing of the wide regions 14a, and as a consequence, wide region 14a comes in contact with the adjacent wide region 14a, so that there are instances in which the copper pattern is completely shorted.
On the other hand, as shown in FIG. 9(b), if the wide regions are not formed on the copper pattern 14 and it has a straight shape, it is possible to make the copper pattern correspond to a narrow pitch. But when the solder powder adhered on top of the copper pattern of this straight shape is reflowed, variations are generated in the positions at which the solder protrudes and in the height at which the solder protrudes, so that positive bonding of the stud bump electrodes of the semiconductor chip to the solder cannot be performed, which produces poor connections.